audio FPAA ASIC for Wafer Space run 3
An audio FPAA (field-programmable analog array) ASIC being developed by Archit3ch for the Wafer Space run 3 tapeout. Work is ongoing to validate the design blocks before the run's deadline; the author hopes for test results on 2nd-run chips that use only 2 edges on the pad ring, which would enable significant area savings.
What it addresses
The Wafer Space run 3 deadline is fast approaching and many design blocks are only partially validated. The author is also awaiting tested chips from the 2nd run that use only 2 edges on the pad ring, which would enable significant area savings.
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audio FPAA ASIC for Wafer Space run 3
An audio FPAA (field-programmable analog array) ASIC being developed by Archit3ch for the Wafer Space run 3 tapeout. Work is ongoing to validate the design blocks before the run's deadline; the author hopes for test results on 2nd-run chips that use only 2 edges on the pad ring, which would enable significant area savings.
Problem: The Wafer Space run 3 deadline is fast approaching and many design blocks are only partially validated. The author is also awaiting tested chips from the 2nd run that use only 2 edges on the pad ring, which would enable significant area savings.
Posted by @Archit3ch · Builder identity supported: @Archit3ch · Original comment ↗